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| Samplify Couples Compression with Converters |
By BDTI, 11/19/2008
 High data rates pose a number of system design challenges. They require lots of I/O and an extremely fast processor or FPGA, they need lots of memory for storage and buffering, and they eat power as data gets shipped all over the system. That’s why, when high-speed data gets to a processor, often the first thing that’s done is to compress it. But what if you could compress the data before it ever gets to the processor and before it gets shipped around the system? What if you could compress it right at the A/D, where the data first comes in? That’s the clever idea that Samplify Systems hopes to build a business on.
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| Freescale Ups the Ante with Six-Core Chip |
By BDTI, 11/19/2008
 Earlier this month Freescale announced that it will be offering a new six-core DSP chip, the MSC8156, that targets wireless infrastructure applications. The chip uses a new DSP processor core, the StarCore SC3850, which is similar to the earlier SC3400 but has (among other enhancements) twice the multiply-accumulate (MAC) throughput – the SC3850 can execute eight 16-bit MACs per cycle rather than four. This is the first new DSP processor product from Freescale in quite a while, and the first such product since Lisa Su took over the reigns of Freescale’s networking and multimedia group from longtime general manager Lynelle McKay. The MSC8156 will be fabbed in a 45 nm process and will be available in two speed grades, 800 MHz and 1 GHz. Freescale expects to sample chips in the first quarter of 2009, with production pricing starting at $192 in 10K quantities.
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| Change for the Better – With the help of BDTI |
By BDTI, 11/19/2008
When is the right time to adopt a new way of doing things? It’s a no-brainer that systems designers have to select a new tool or component when the one they’ve been using is obsoleted. But should a company adopt a new design methodology when the one they’re using still works? After all, “if it ain’t broke, don’t fix it”—right? Well, maybe.
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| Jeff Bier's Impulse Response—We’re Sorry, You’ve Been Disconnected |
By Jeff Bier, 11/19/2008
A few years back I flew to Boston for a conference. Since I have a well-founded fear of driving in Boston, I rented a car with GPS navigation. I drove out of the airport and checked the GPS system, which was functioning perfectly. A short time later, I headed into a tunnel. Suddenly, there were exits coming up fast (inside the tunnel!), and I wasn’t sure which one to take. I looked to my navigation system for guidance, but it was completely clueless. Having lost the GPS signal when I entered the tunnel, the system refused to give me any route information.
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| Texas Instruments Introduces Triple-Core ‘C6474 |
By BDTI, 10/15/2008
 On October 14, 2008, Texas Instruments introduced a high-performance multi-core DSP, the TMS320C6474 that is intended for use in computationally demanding applications such as communications infrastructure, video surveillance, and medical imaging. The chip features three 1 GHz ‘C64x+ cores, each with its own L1 data and program cache, along with 3 MBytes of aggregate (not shared) L2 cache. As shown in Figure 1, the chip also contains a Viterbi accelerator and turbo decoding accelerator along with a DDR interface, an antenna interface, an Ethernet port, and a McBSP serial port. The chip is fabbed in a 65 nm process and costs $225 in 1K quantities. TI is also offering an evaluation module that contains two ‘C6474 chips for $1,995.
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| Percello Puts Cellular Femtocell Baseband on a Chip |
By BDTI, 10/15/2008
 Fabless semiconductor start-up Percello, is hoping to find success in the UMTS (cellular) femtocell market by offering a highly integrated SoC for baseband processing. Today, femtocell baseband processing is typically handled by a combination of processors and FPGAs, but Percello believes that the potential for high volumes means that a cheaper, simpler solution is needed. The company’s initial product, the PRC6000 baseband chip, is designed to serve as a standalone femtocell processor and as a subsystem element for a residential gateway. The chip will be fabbed in a 65 nm process and tape-out is expected by the end of this year, with initial samples becoming available in the first quarter of 2009. Pricing has not been disclosed, though Percello claims that its chip price will be a key competitive advantage relative to DSP-plus-FPGA or SDR silicon-based solutions.
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| Case Study - Improving Chip Architectures with Specialized Talent |
By BDTI, 10/15/2008
In an ideal world, chip designers would evaluate their new designs on real applications. But who’s got the time to implement an entire cellular baseband or video codec just to see if their proposed design is efficient? That’s the reason chip designers use benchmarks. But benchmarking is not just about selecting the right algorithms. It’s also about careful implementation—careful crafting of software that is appropriately optimized for the target architecture. As a result, sound benchmarking is a time-consuming activity. That’s why many chip companies come to BDTI; not only for BDTI’s benchmarks, but often to have their own—or their customers’—benchmarks implemented by BDTI’s expert engineering staff.
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| Jeff Bier's Impulse Response—System-in-Package Will Bring Variety, Efficiency |
By Jeff Bier, 10/15/2008
Last month I wrote about how my colleagues and I believe that embedded processor vendors will need to become more involved in developing or acquiring proprietary algorithms to stay competitive in the coming decade. This month, I’ll discuss another long-term trend that we expect to see in processor-based chips: the dramatically expanded use of multi-die packaging (also called “system-in-package”).
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| BDTI Releases Benchmark Results for Tilera’s TILE64 Multicore Processor |
By BDTI, 9/17/2008
Note: This article has been changed on 09/26/2008 from its original version.
 BDTI has released independent benchmark results for Tilera’s massively parallel TILE64 processor on the BDTI Communications Benchmark (OFDM)™. The TILE64 chip incorporates 64 processor cores connected to each other in a mesh configuration. The cores operate at 866 MHz and are fairly simple, three-issue VLIW machines that support limited SIMD operations, such as SIMD adds and subtracts (but not SIMD multiplies). Tilera expects engineers to program the chip using C/C++ along with intrinsics to access the SIMD capabilities.
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| Fraunhofer Stealthily Advances Compression Technologies |
By BDTI, 9/17/2008
 There’s a German research institution that many people outside of Europe have never heard of. Well, there are probably lots of German research institutions that many people have never heard of, but this particular one, Fraunhofer, was instrumental in developing a technology that millions of people use every day—a little thing called MP3. Fraunhofer also co-developed AAC and has been involved in developing the H.264 video codec, along with other codecs. But unlike the audio algorithm experts at Dolby, whose brand is visible on home audio equipment and whose name is nearly synonymous with high-quality audio, Fraunhofer has kept a relatively low profile. That’s because it has a somewhat unusual business model and history.
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