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| Synfora’s PICO High-Level Synthesis Tool Achieves BDTI Certification |
By BDTI, 3/18/2010
 BDTI recently completed an in-depth evaluation of Synfora’s PICO tool through the BDTI High-Level Synthesis Tool Certification Program™. BDTI evaluated the process of implementing applications on a Xilinx FPGA using PICO, comparing it with traditional FPGA design based on hand-written RTL code, and with DSP processor software development. PICO enabled creation of efficient FPGA implementations, with design productivity comparable to that of DSP processor software development. The algorithmic C code required fewer modifications than the code that was used to implement the design on a DSP processor, while providing over a 30X improvement in price/performance.
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| FPGA Start-Up Tabula Exits Stealth Mode, Unveils “3-D” Architecture and First Devices |
By BDTI, 3/18/2010
 FPGA start-up Tabula recently emerged from stealth mode and disclosed details of its architecture, dubbed Spacetime, and product line, called the ABAX family. Tabula’s products are intended to compete against existing high-end FPGAs by offering higher density with the same design methodology. Tabula is initially aiming its chips at network, wireless, and telecom infrastructure markets–all sweet spots for programmable logic. These markets are characterized by a need for programmability due to rapidly changing standards, unit volumes too small to attract ASSP or ASIC competition, and relatively high gross margins for semiconductor suppliers.
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| Jeff Bier's Impulse Response: Change or Be Changed |
By Jeff Bier, 3/18/2010
We’re on the cusp of profound changes in the competitive landscape for embedded processing engines—changes that I believe will “shuffle the deck” with respect to which kinds of architectures are dominant in many applications.
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| Case Study: Maximizing DSP Software Performance on ARM Processors |
By BDTI, 3/18/2010
A decade ago, ARM processors were mainly found in cell phones, disk drives, and few other specialized applications. These days, they seem to be everywhere, from microcontrollers to tablet PCs. During this same time period, digital signal processing (DSP) tasks—such as multimedia and communications functions—have also become increasingly common in a wide range of systems. Given these two trends, it’s no surprise that there’s been a big uptick in products using ARM processors to implement digital signal processing tasks.
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| AutoESL’s AutoPilot High-Level Synthesis Tool Achieves BDTI Certification |
By BDTI, 2/16/2010
 BDTI recently completed an in-depth analysis of AutoESL’s AutoPilot high-level synthesis tool via the BDTI High-Level Synthesis Tool Certification Program™. BDTI evaluated the process of implementing applications on a Xilinx FPGA using AutoPilot, comparing it with traditional FPGA design based on hand-written RTL code, and with DSP processor software development. Overall, AutoPilot demonstrated a strong ability to generate high-quality RTL code—with equivalent resource utilization to hand-written RTL code.
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| Texas Instruments Introduces New Multi-Core System-on-Chip Architecture |
By BDTI, 2/16/2010
 TI has unveiled a new chip-level architecture for high-performance, multi-core DSP-processor-based SoCs. Most notable among its features are new on-chip and chip-to-chip interconnection mechanisms, an upgraded high-performance DSP core, and both hardware and tools support for programming concurrent applications. The architecture is optimized to run at 1.0 to 1.2 GHz in 40 nm process technology.
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| Jeff Bier's Impulse Response: Compilers Can Erase Architectural Advantages |
By Jeff Bier, 2/16/2010
Back in the early 1990’s, compilers for DSP processors were pretty lame. Even if a compiler generated code that was functionally correct (which, sadly, wasn’t always the case) the code was usually far from efficient. At the time, this wasn’t a big deal: DSP applications were still fairly small (in terms of lines of code), and DSP processor architectures weren’t nearly as complex as they are today. A reasonably skilled DSP software engineer could optimize an application by hand, sometimes entirely in assembly language, without using a compiler at all.
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| Case Study: Developing Attention-Getting Demos |
By BDTI, 2/16/2010
Your company just developed the most powerful chip ever. Your job: to get customers interested in using it in their system designs. Challenging? You bet. As fantastic as its capabilities may be, your little slab of black plastic looks pretty much just like those of your competitors. Yes, the numbers on your brochure look great. But, let’s face it, they’re just numbers on paper. How exciting can they be?
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| BDTI Unveils High-Level Synthesis Tools Certification Program Results |
By BDTI, 1/20/2010
 This week BDTI released the first results from its High-Level Synthesis Tools Certification Program (HLSTCP). The first tools to achieve certification are AutoESL’s AutoPilot and Synfora’s PICO. Additional certifications will be released on an ongoing basis, as agreements with tool vendors allow. The HLSTCP helps engineers and managers understand the capabilities of high-level synthesis (HLS) tools and assess when to consider these tools for their designs. HLS tool vendors can use the program to validate and improve the quality of results and productivity provided by their tools. (HLS tools are also referred to as electronic system level [ESL] synthesis, C synthesis, behavioral synthesis, or algorithmic synthesis tools.)
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| New ADI Blackfin Integrates Large Executable Flash for Control Applications |
By BDTI, 1/20/2010
 Analog Devices, Inc. (ADI) has announced new members of the Blackfin processor family targeting control-loop applications. The new BF50x parts sport a much larger “executable” flash in place of the serial flash offered in earlier Blackfin chips, and integrate a 12-bit analog-to-digital converter suitable for control applications.
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