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Texas Instruments Introduces Triple-Core ‘C6474 By BDTI, 10/15/2008 On October 14, 2008, Texas Instruments introduced a high-performance multi-core DSP, the TMS320C6474 that is intended for use in computationally demanding applications such as communications infrastructure, video surveillance, and medical imaging. The chip features three 1 GHz ‘C64x+ cores, each with its own L1 data and program cache, along with 3 MBytes of aggregate (not shared) L2 cache. As shown in Figure 1, the chip also contains a Viterbi accelerator and turbo decoding accelerator along with a DDR interface, an antenna interface, an Ethernet port, and a McBSP serial port. The chip is fabbed in a 65 nm process and costs $225 in 1K quantities. TI is also offering an evaluation module that contains two ‘C6474 chips for $1,995. (More)

Percello Puts Cellular Femtocell Baseband on a Chip By BDTI, 10/15/2008 Fabless semiconductor start-up Percello, is hoping to find success in the UMTS (cellular) femtocell market by offering a highly integrated SoC for baseband processing. Today, femtocell baseband processing is typically handled by a combination of processors and FPGAs, but Percello believes that the potential for high volumes means that a cheaper, simpler solution is needed. The company’s initial product, the PRC6000 baseband chip, is designed to serve as a standalone femtocell processor and as a subsystem element for a residential gateway. The chip will be fabbed in a 65 nm process and tape-out is expected by the end of this year, with initial samples becoming available in the first quarter of 2009. Pricing has not been disclosed, though Percello claims that its chip price will be a key competitive advantage relative to DSP-plus-FPGA or SDR silicon-based solutions. (More)

Case Study - Improving Chip Architectures with Specialized Talent By BDTI, 10/15/2008 In an ideal world, chip designers would evaluate their new designs on real applications. But who’s got the time to implement an entire cellular baseband or video codec just to see if their proposed design is efficient? That’s the reason chip designers use benchmarks. But benchmarking is not just about selecting the right algorithms. It’s also about careful implementation—careful crafting of software that is appropriately optimized for the target architecture. As a result, sound benchmarking is a time-consuming activity. That’s why many chip companies come to BDTI; not only for BDTI’s benchmarks, but often to have their own—or their customers’—benchmarks implemented by BDTI’s expert engineering staff. (More)

Jeff Bier's Impulse Response—System-in-Package Will Bring Variety, Efficiency By Jeff Bier, 10/15/2008 Last month I wrote about how my colleagues and I believe that embedded processor vendors will need to become more involved in developing or acquiring proprietary algorithms to stay competitive in the coming decade.  This month, I’ll discuss another long-term trend that we expect to see in processor-based chips: the dramatically expanded use of multi-die packaging (also called “system-in-package”). (More)