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ARC Previews Powerful Media Extensions By BDTI, 11/7/2005 Last week processor core licensor ARC introduced a multimedia subsystem for its ARC 700 family of configurable cores.  The most notable feature of this subsystem is the SIMD engine.  This engine features a 128-bit-wide data path that can perform up to sixteen 8-bit operations, eight 16-bit operations or four 32-bit operations per cycle. (More)

Video Benchmarking By BDTI, 11/7/2005 Digital video has emerged as one of the hottest markets for DSPs and other types of processors. As a result, many processors now target digital video applications. However, not every processor is up to the challenge.  Digital video applications have heavy computation and memory-bandwidth loads, so it’s critical to choose a processor that can handle those demands.  For this reason, system and SoC designers who are evaluating processors for digital video applications are strongly motivated to obtain credible video-oriented performance data. (More)

Jeff Bier’s Impulse Response – Suboptimal Optimization By Jeff Bier, 11/7/2005 The complexity of a processor’s core architecture has a significant impact on how difficult it will be to optimize the code. But more and more, it’s critical to also consider the complexity of the whole chip. I was recently (and painfully) reminded of this fact a few months ago when my colleagues and I set out to optimize some video software for an ARM9E-based SoC. (More)

Latest StarCore Architecture Promises More Speed By BDTI, 11/7/2005 Last week StarCore unveiled the first details of its next-generation DSP core family, the SC3000.  The most notable new feature is the family’s high clock rate: According to StarCore, SC3000 cores will achieve a clock rate of 1 GHz in a high-performance 90 nm process.  In comparison, StarCore claims that SC2000 cores can achieve clock rates of about 600 MHz under the same conditions.  StarCore has also boosted the SC3000’s performance with a variety of new instructions. (More)