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Inside DSP on Low Power: Processors for Low-Power Signal Processing
By , 6/1/2004

In many low-power applications, the processor is a major contributor to the overall system energy consumption. Hence, the processor typically plays a key role in determining a product's battery life. The choice of processor also affects many other critical aspects of the system, such as price and performance. In this article we explore processor options for low-power signal processing applications. We begin with a discussion of the criteria to consider when selecting a processor for a low-power signal processing application. Next, we highlight energy-efficient architectural approaches. We then describe the categories of processors used in low-power signal processing applications and explore the strengths and weaknesses of each category. Finally, we take a close look at a new category of high-performance, energy-efficient chips known as "application processors."

Selection criteria
Maximizing battery life is a top priority for most low-power applications. Typically, a processor's run-mode energy efficiency and its standby-mode power consumption play key roles in determining battery life. On-chip integration, particularly the size of on-chip memory, also plays a key role in determining battery life. Off-chip transactions such as memory accesses consume far more power than equivalent on-chip transactions. Hence, increasing on-chip integration tends to increase energy efficiency. A processor must also provide the right speed and cost for the application. And it is not enough for the processor itself to be inexpensive; the processor must enable an inexpensive overall system design. This typically implies that the processor must include substantial on-chip memory and peripherals.

Energy-saving tactics
Processor designers use a wide variety of techniques to maximize battery life. In this section we briefly discuss three key techniques: processor parallelism, data type selection, and operating mode flexibility. "Designing Low-Power Signal Processing Systems," provides further detail on these techniques and describes others not covered here.

Parallelism plays a particularly important role in determining processor energy efficiency. By using a higher level of parallelism, a processor can accomplish more work per clock cycle. Hence a higher level of parallelism allows a processor to operate at a lower clock speed, which in turn enables use of a lower supply voltage. As explained in "Designing Low-Power Signal Processing Systems," processors can achieve significant energy efficiency gains by operating at lower voltages. Therefore processors with high levels of parallelism tend to achieve better energy efficiency than processors with low levels of parallelism. Of course, higher parallelism only leads to better energy efficiency when the application can make use of the parallelism.

Perhaps the simplest means to achieve higher parallelism is by using a processor architecture that can perform multiple operations per clock cycle. One particularly effective way to do this is to encode multiple parallel operations in each instruction. For example, most processors targeting signal processing applications provide a multiply-accumulate (MAC) instruction that performs both a multiply and an addition. A related approach is to design the processor to execute multiple instructions in parallel. This provides more flexibility in terms of the operations that can be performed in parallel, but it comes at the cost of increased energy consumption.

Another subtle but important way to increase parallelism is the use of "smart" peripherals such as direct memory access (DMA) controllers. A DMA controller can move data between various processor resources without intervention from the processor, which frees the processor to perform other tasks—or to remain in a low-power standby mode.

In many low-power applications, the processing load varies dramatically over time. Consider the processing requirements of a cell phone: in standby mode, the phone only requires a modest amount of processing to "listen" for an occasional incoming call. In contrast, the phone requires significant processing speed in talk mode. Similarly, the demands on the peripherals and other processor resources may vary over time.

In recognition of these varying demands, processors targeting low-power applications typically offer multiple operating modes. Some processors offer only two modes: a fully-on "active" mode and an idle mode that disables the clock signal to the processor core but leaves the peripherals running. Other processors give the system designer more options. For example, some processors allow the system designer to enable or disable individual peripherals. Such flexibility is desirable because it lets system designers use only the processor resources needed at any given time.

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