Technology improvements, such as low-voltage chips, help reduce energy consumption for a given set of system features and level of performance. But system features and performance are moving targets: typically, with each product generation designers must integrate additional energy-consuming features and deliver even higher performance in an ever-shrinking space. This creates an energy efficiency crunch. And, unfortunately, battery technologies tend to improve at a maddeningly slow pace compared to other electronic technologies. As shown in Table 1, the latest lithium ion batteries offer only a three-fold improvement in storage density over nickel cadmium batteries—which were invented in 1899!

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A variety of design techniques can reduce energy consumption in a signal processing system. These range from new low-power chip fabrication techniques to energy-aware software design. Although many of the ideas covered in this article are applicable to a broader range of low-power electronic systems, we focus on techniques for processor-based embedded systems aimed at signal processing-intensive applications.

Low-Power Chip Design
Processors, memories, and other silicon components consume a significant portion of the total system energy in a typical battery-powered device. Thus, they are an obvious place to start when beginning to optimize a design for low energy consumption.

The dominant digital chip fabrication technology is CMOS—complimentary metal oxide semiconductor. One interesting feature of a CMOS logic gate is that it consumes very little energy when idle. In contrast, when a CMOS logic gate transitions between states (for example, switching from 0 to 1) it consumes much more energy. This means that designers can save lots of energy if they can keep the majority of a CMOS chip inactive. (As we discuss later, this situation is changing with the latest emerging fabrication processes, where idle power consumption is becoming a much larger factor.)

Calculating CMOS Power
A simplified equation for power consumption in a CMOS gate is P = C_LV²f + I_qV, where C_L is the load capacitance, V is the supply voltage, I_q is the leakage current, and f is the switching frequency.

The first part of the equation, C_LV²f, describes the dynamic power that is dissipated in a CMOS gate as it switches. To illustrate this concept, Figure 1 shows a diagram of two CMOS inverters, one with an input of 3.3 volts, the other with an input of 0 volts. The output of an inverter is the "opposite" of the input: each time the input voltage switches from 3.3 to 0 volts, the output switches correspondingly from 0 to 3.3 volts. Energy is consumed primarily when the output switches. Any CMOS gate has a load capacitance C_L associated with its output. Driving this load capacitance from 0 to 3.3 volts requires energy and this is where dynamic CMOS power is consumed.