By BDTI, 10/11/2004
This month both ARM and MIPS announced new
signal-processing-oriented instruction set extensions for their future
processor lineups. ARM’s extensions, which it calls NEON, will greatly
expand the signal processing capabilities of the ARM architecture. NEON
will add a register file organized as 32 64-bit registers or 16 128-bit
registers. NEON will operate on these registers using
single-instruction multiple-data (SIMD) operations that treat each
register as packed 8-, 16-, 32-, or 64-bit data. For example, NEON will
offer an instruction that performs four 16-bit multiplications on data
packed into 64-bit registers and then stores the four 32-bit results in
a 128-bit register. NEON has support for integer, fractional, and
single-precision floating-point data.
Interestingly, NEON appears to be quite
similar to Intel’s Wireless MMX, which is Intel’s multimedia extension
for its ARM-compatible XScale architecture. Both NEON and Wireless MMX
have separate register files and add a variety of SIMD-oriented
instructions. However, NEON and Wireless MMX differ in several
important ways. For example, NOEN supports single-precision
floating-point operations, but Wireless MMX does not. (For more
information on Wireless MMX, see the October 2002 DSP Insider.)
In the last few years, ARM has gradually increased the DSP
functionality of its architectures. It appears that NEON will raise the
signal-processing horsepower of the ARM cores to a level comparable to
that of many mainstream DSPs. However, ARM has released only limited
information about NEON, and its capabilities in many areas are unknown.
For example, signal-processing applications tend to place significant
demands on memory bandwidth, but ARM has not disclosed the details of
the memory buses of its future NEON-enhanced cores.
The MIPS instruction set extension, the DSP ASE
(application-specific extension), is intended for use in MIPS’ 32-bit
and 64-bit architectures. A 32-bit implementation of the DSP ASE will
support up to four 8-bit, two 16-bit, or one 32-bit operation using a
single instruction. With the exception of three accumulators and new
control registers, the DSP ASE adds no additional registers to the MIPS
architecture. MIPS states that the DSP ASE will add less than 6% to the
die area of its processors.
Unlike ARM, in the past MIPS has put little emphasis on
signal-processing features. However, the DSP ASE will give the MIPS
architectures signal-processing capabilities comparable to those of
existing DSP-enhanced GPP cores. For example, the functionality of a
32-bit implementation of the DSP ASE will be roughly comparable to
those of the ARM11 (which does not include the new NEON extensions).
Neither ARM nor MIPS have announced any cores that include their new DSP-oriented instruction extensions.
|