By BDTI, 11/7/2005
Last week StarCore unveiled the first details
of its next-generation DSP core family, the SC3000. The most notable
new feature is the family’s high clock rate: According to StarCore,
SC3000 cores will achieve a clock rate of 1 GHz in a high-performance
90 nm process. In comparison, StarCore claims that SC2000 cores can
achieve clock rates of about 600 MHz under the same conditions. (The
clock speeds quoted in this article assume nominal silicon under
worst-case voltage and temperature variations. In contrast, chip
designs usually assume slow silicon under worst-case voltage and
temperature variations. StarCore has not announced SC3000 clock speeds
for slow silicon, but these speeds are likely to be 20-30% lower than
speeds for nominal silicon.)
The higher clock speed is enabled by use of a longer pipeline. The
SC3000 will use a twelve-stage pipeline—twice the length of the
pipeline in its predecessor, the SC2000. The SC3000 pipeline will also
be longer than the pipelines in most competing processors.
Although the long pipeline enables a higher
clock rate, it also presents new challenges. Processors with long
pipelines typically have long instruction latencies. Among other
problems, these long instruction latencies can reduce processor
efficiency and complicate code optimization. Fortunately, StarCore has
taken steps to address these challenges. Most importantly, StarCore has
maintained single-cycle latencies for load-execute and execute-store
sequences.
StarCore has also boosted performance with a variety of new
instructions. The most notable of these instructions are new
instructions that accelerate Viterbi decoding, a key algorithm used in
communications applications. According to StarCore, these new
instructions reduce the cycles needed for Viterbi decoding by a factor
of 2.5. BDTI has not evaluated this claim, but it has implemented the
BDTI Viterbi Decoder benchmark on the SC1400. BDTI found that the
SC1400 was very efficient on this benchmark—only a few other processors
can complete the benchmark in fewer cycles. Improving this result by a
factor of 2.5 would be a remarkable accomplishment.
The SC3000 cores will also add a memory management unit (MMU) that will
enable the cores to run full-featured OSs such as Linux. This feature
will give the SC3000 a significant advantage because few other DSPs
include an MMU. The SC3000 will be particularly attractive for some
applications that currently require both a DSP and a general-purpose
processor. In such applications, it will often be possible to replace
both cores with a single SC3000.
Although StarCore has not released the full details of the SC3000
cores, it is clear that these cores will greatly increase the
capabilities of StarCore’s lineup. StarCore plans to announce specific
SC3000 cores in mid-2006. BDTI looks forward to performing a more
detailed analysis at that time.
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