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| Texas Instruments Focuses on Low Power with New Chips |
By BDTI, 7/23/2008
 In July, Texas Instruments announced that it will offer new low-power variants of four of its key DSP processor product lines: the ’C55x, the ’C64x+, the ’C67x, and OMAP. The new family members are intended to span a wide range of low-power applications, from those that are line-powered but require low heat dissipation (such as home entertainment gear, where cooling fans are considered too noisy) to those that require a week or more of battery life (such as portable medical monitoring devices).
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| TI Launches Low-Cost DaVinci Processor with HD Video Capability |
By BDTI, 9/26/2007
 This month Texas Instruments launched the DM355, the latest chip in its “DaVinci” family. The DM355 supports high-definition MPEG‑4 video encoding and decoding (but not both simultaneously) and is intended for low-cost imaging and video applications such as digital still cameras, IP video cameras, digital photo frames and video baby monitors.
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| ARC Introduces Configurable Video Subsystems |
By BDTI, 8/22/2007
 Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.
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| Atmel Announces CAP Customizable Microcontrollers |
By BDTI, 7/18/2007
 In June Atmel announced the Customizable Atmel Processor (CAP), a family of customizable microcontrollers, and two initial devices. Customization in the CAP is achieved via a gate array block in which users can implement functions ranging from processor cores and peripherals to algorithm accelerators.
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| CEVA Announces 32-bit, Dual-MAC TeakLite-III DSP Core |
By BDTI, 6/20/2007
Note: This article has been changed on 07/18/2007 from its original version.
 On May 31, CEVA Inc. announced CEVA-TeakLite-III, a new family of DSP cores. To meet the precision and throughput demands of its intended applications, which include high-end audio, 3G cellular, VoIP, and portable audio players, the TeakLite-III features support for both 32-bit and 16-bit fixed-point data, and increased MAC throughput relative to CEVA’s earlier TeakLite cores.
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| CEVA Unveils “Lite” Mobile Multimedia Platform |
By BDTI, 4/25/2007
 In March CEVA unveiled “Mobile-Media-Lite” (MMLite), a family of multimedia solutions comprising licensable silicon IP and software. The family is aimed at low-end multimedia-enabled devices such as mobile TV players, portable multimedia players, and multimedia phones. CEVA also announced the first family member, the MM2200, a single-processor multimedia platform.
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| Xilinx Spartan gets DSP |
By BDTI, 4/25/2007
 In recent years, FPGA vendors have been aggressively pursuing high-performance signal processing applications. This month Xilinx broadened its target DSP markets by announcing a new lower-cost DSP-oriented FPGA family, Spartan-3A DSP.
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| Jeff Bier’s Impulse Response – Efficiency Comes in Many Flavors |
By Jeff Bier, 4/25/2007
It’s generally accepted that, for processing engines, there is a trade-off between efficiency and generality. The more a chip is geared towards a specific application, the more efficient it's likely to be (in terms of speed, energy consumption, and cost).
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| Stretch Announces Second-generation Software Configurable Processor |
By BDTI, 3/14/2007
 On March 5, Stretch, Inc. announced its second-generation software configurable processor family, the S6000, and two initial chips. The S6000, like the previous-generation S5000 family, features a RISC processor core with a reconfigurable compute fabric embedded within the processor datapath.
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| Stream Processors Unveils Data-parallel Processor Architecture |
By BDTI, 2/14/2007
 Stream Processors, Inc. (SPI) this week unveiled its data-parallel processor architecture and announced two chips based on the architecture. According to SPI, its architecture is optimized for compute-intensive embedded applications which exhibit a high degree of data parallelism, such as video and imaging. SPI believes that cost-performance and developer productivity advantages will enable its chips to compete successfully against FPGAs, high-end DSPs, and ASICs in these applications.
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