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| Texas Instruments Introduces New Multi-Core System-on-Chip Architecture |
By BDTI, 2/16/2010
 TI has unveiled a new chip-level architecture for high-performance, multi-core DSP-processor-based SoCs. Most notable among its features are new on-chip and chip-to-chip interconnection mechanisms, an upgraded high-performance DSP core, and both hardware and tools support for programming concurrent applications. The architecture is optimized to run at 1.0 to 1.2 GHz in 40 nm process technology.
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| New ADI Blackfin Integrates Large Executable Flash for Control Applications |
By BDTI, 1/20/2010
 Analog Devices, Inc. (ADI) has announced new members of the Blackfin processor family targeting control-loop applications. The new BF50x parts sport a much larger “executable” flash in place of the serial flash offered in earlier Blackfin chips, and integrate a 12-bit analog-to-digital converter suitable for control applications.
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| MIPS Launches MicroMIPS Architecture with Two New Cores |
By BDTI, 12/16/2009
 This month MIPS introduced two new cores, the M14K and M14Kc, that are based on a new instruction set architecture called microMIPS. MicroMIPS uses a mixed-width 16/32-bit instruction set to improve code density relative to the MIPS32 instruction set architecture. In general, processors with smaller program memory requirements require less on-chip and off-chip memory, and less memory bandwidth. This can translate into reduced cost and power consumption. Since cost and power are key metrics for many embedded applications, 16-bit compressed instruction sets have become fairly common.
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| CEVA Simplifies DSP Software Development |
By BDTI, 12/16/2009
 This month CEVA announced significant improvements to its software tool suite. Collectively, the new tools and features are dubbed the CEVA Application Optimizer, and are part of the CEVA-Toolbox software development suite. CEVA describes these capabilities as providing an “end-to-end, fully C-based development flow.” This is an important topic for users of DSP processors, who are less and less willing to write heavily target-specific C code or assembly code which requires them to become architecture experts.
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| Jeff Bier's Impulse Response—NVIDIA GPUs Turn Up the Heat |
By Jeff Bier, 12/16/2009
In October of 2007, I wrote a column called “When Worlds Collide,” which was about NVIDIA’s emerging strategy of offering “general-purpose GPUs.” At the time, I thought it was interesting that NVIDIA had begun to move beyond graphics applications to target “high-performance computing” (HPC) applications like financial and seismic analysis, thus competing with processors outside of the GPU space. I also observed that the ubiquity of GPUs in PCs would likely help NVIDIA gain traction in non-GPU applications.
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| Multicore Heats up with Chip Announcements from TI, Tilera |
By BDTI, 11/18/2009
 Recently both Texas Instruments and Tilera announced new multicore chips. TI announced the TMS320C6472, which includes six ‘C64x+ processor cores running at 500-700 MHz (depending on the family member). Tilera announced a new chip family, the TILE-Gx, which will include variants with 16-100 cores running at 1.25-1.5 GHz. The ‘C6472 is available now, while Tilera does not expect to start sampling TILE-Gx chips until late 2010. According to Tilera, TILE-Gx chips will be fabbed in a 40 nm process. These announcements represent two of the common approaches to multicore today: putting a handful of processors that were originally designed for standalone use on a single die (TI) and creating a new architecture incorporating numerous cores (Tilera).
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| Quartics Announces Flexible Video Chip |
By BDTI, 11/18/2009
 This month fabless semiconductor start-up Quartics introduced the QV1721, a video coprocessor SoC targeting applications such as netbook PCs, set-top boxes and high-definition televisions. The QV1721 is intended to be used to offload demanding video tasks from the main CPU in a system. The chip provides high-definition video encoding, decoding, and transcoding functions, along with post-processing to improve perceived video quality.
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| Jeff Bier's Impulse Response—Creative Tools Key to DSP on MCUs |
By Jeff Bier, 10/21/2009
The beauty of digital signal processing is that it enables people to convert available processing power into cool new features, better performance, and lower power in their products. There are countless examples, including MP3 players, wireless communications of all kinds, medical imaging, and voice recognition.
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| ARM Announces 2 GHz Dual-Core Cortex-A9 |
By BDTI, 9/23/2009
 On September 21st ARM announced a new high-speed, hard macro implementation of the Cortex-A9 architecture, called “Osprey.” (A hard macro is a physical implementation of an IP block in a specific process.) Osprey is a dual-core implementation of the Cortex-A9 and according to ARM, it will run at up to 2 GHz in a 40 nm (TSMC 40G) fabrication process. Like other Cortex-A9 variants, Osprey includes a floating-point unit (FPU) and NEON SIMD signal processing unit for each core.
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