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| AutoESL’s AutoPilot High-Level Synthesis Tool Achieves BDTI Certification |
By BDTI, 2/16/2010
 BDTI recently completed an in-depth analysis of AutoESL’s AutoPilot high-level synthesis tool via the BDTI High-Level Synthesis Tool Certification Program™. BDTI evaluated the process of implementing applications on a Xilinx FPGA using AutoPilot, comparing it with traditional FPGA design based on hand-written RTL code, and with DSP processor software development. Overall, AutoPilot demonstrated a strong ability to generate high-quality RTL code—with equivalent resource utilization to hand-written RTL code.
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| BDTI Unveils High-Level Synthesis Tools Certification Program Results |
By BDTI, 1/20/2010
 This week BDTI released the first results from its High-Level Synthesis Tools Certification Program (HLSTCP). The first tools to achieve certification are AutoESL’s AutoPilot and Synfora’s PICO. Additional certifications will be released on an ongoing basis, as agreements with tool vendors allow. The HLSTCP helps engineers and managers understand the capabilities of high-level synthesis (HLS) tools and assess when to consider these tools for their designs. HLS tool vendors can use the program to validate and improve the quality of results and productivity provided by their tools. (HLS tools are also referred to as electronic system level [ESL] synthesis, C synthesis, behavioral synthesis, or algorithmic synthesis tools.)
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| Synphony Synthesis Tool Takes MATLAB to RTL |
By BDTI, 10/21/2009
 High-level synthesis tools (i.e., tools that take high-level language code and generate an RTL-based hardware implementation) have been around a long time, but historically they have had limited success in the market. The primary problems have been that they have been hard to use and have generated relatively inefficient implementations. But their potential advantages are compelling, particularly as applications become more complicated: in the best case they can reduce implementation time and errors, and possibly reduce the need for RTL experts. For these reasons, a number of vendors have introduced high-level synthesis tools in recent years, including AccelChip (later acquired by Xilinx), Mentor Graphics, Cadence, AutoESL, and Synfora, among others. Most of these take C representations as inputs and synthesize them into RTL for FPGA or ASIC implementation, though some have promised MATLAB to RTL.
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| Xilinx Intros Spartan-6, Virtex-6; Promises App-Specific Development Support |
By BDTI, 2/18/2009
 Xilinx recently introduced two new FPGA chip families, Spartan-6 and Virtex-6, that offer increased capacity and lower power consumption relative to their predecessors. For the first time, the new Spartan and Virtex families use the same underlying architecture to enable easier migration. There are, however, differences in fabrication process and features. Spartan-6 chips will be fabbed in a 45 nm process, while Virtex-6 chips will be fabbed in 40 nm. Spartan-6 chips incorporate DDR3 integrated memory controllers and support for 3.3-volt I/O; Virtex-6 chips include specialized FIFO logic, tri-mode EMAC, and System Monitor. (The System Monitor is a debug and thermal management tool that was introduced in Virtex-5.)
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| Xilinx Debuts Virtex-5 FXT, Expands SXT Platform |
By BDTI, 5/28/2008
 At the end of March, Xilinx announced availability of the first two members of its Virtex-5 FXT platform, the FX30T and FX70T. The Virtex-5 FXT platform is geared towards serial communications and embedded applications, and joins three other Virtex-5 platforms: the LX, which is intended for logic-intensive applications; the LXT, which targets logic and serial communications; and the SXT, which is intended for serial communications and DSP. (The “T” in the platform name indicates that the chips contain transceivers.) Target applications for the new FXT chips include video-over-IP, wireless base stations, and other high-performance applications.
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| Altera Jumps to 40 nm with Stratix IV |
By BDTI, 5/28/2008
 Not to be outdone by rival Xilinx, Altera has made a major announcement of its own. In mid-May, Altera unveiled its next-generation high-performance FPGA family, the Stratix IV, and announced that the family will be fabbed in a 40 nm TSMC process. Xilinx beat Altera to the 65 nm node with its Virtex-5 chips, but with this announcement, it appears that Altera will leapfrog Xilinx to 40 nm—assuming that Xilinx doesn’t come out with 40 nm chips before the Stratix IV is expected to start sampling, towards the end of this year.
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| Case Study: Where Does Your Processing Engine Fit In? |
By BDTI, 4/23/2008
Developing a new signal processing engine is expensive and risky, particularly for a small start-up or for an established company moving into an unfamiliar market. There are good reasons to take that risk: signal processing has become ubiquitous in a wide range of application areas, and offers the potential for high revenues. The flip side is that the market is already densely populated with all kinds of signal processing engines: single-core chips, multi-core chips, massively parallel processors, DSP-enhanced FPGAs, SoCs, etc. Depending on the specific target market, a new processor may find itself going head-to-head with some or all of these classes of competitor.
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| Catalytic Acquires Celoxica’s C-to-FPGA Tools |
By BDTI, 1/23/2008
 Catalytic recently acquired Celoxica's ESL business. Catalytic already offers a MATLAB-to-C tool, and with the acquisition of Celoxica's C-to-FPGA tool, the company is poised to deliver seamless MATLAB-to-FPGA translation.
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