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Xilinx Announces Next-Generation 28 nm FPGA Families By BDTI, 7/29/2010 Xilinx recently announced its next-generation “7 series” FPGAs, featuring new power-saving features as well as increased capacity and performance.  The series will be composed of three chip families, all fabricated in TSMC’s high-k metal gate (HKMG) 28 nm technology.  All three families will use the same logic cells, block RAMs, DSP slices, and I/O cells.  Compared to existing 40 nm Xilinx devices, Xilinx claims that, in typical applications, the new FPGAs will reduce power consumption by 50, deliver the same performance at 50% lower cost, or offer twice the performance in a single chip.  The forthcoming ARM-based CPU-FPGA platform described here will be part of the new 7 series FPGAs. (More)

Altera Announces Variable-Precision DSP Blocks in Stratix V FPGAs By BDTI, 6/29/2010 Altera recently disclosed architecture details of its next generation Stratix V FPGA family.  The architecture features a variable-precision DSP block, designed to provide better resource utilization for algorithms requiring a variety of data widths. (More)

Xilinx Unveils High-Performance ARM-based CPU-FPGA Hybrid Platform By BDTI, 5/20/2010 Xilinx recently unveiled a new chip architecture integrating an ARM processor with an FPGA fabric. This platform centers around a dual-core ARM Cortex-A9 processor complex, including hardened memory interfaces and peripherals.  The platform architecture, shown in Figure 1, is intended to behave like a CPU first and an FPGA second.  Specifically, the CPU will boot independently—without requiring that the FPGA first be configured.  Xilinx is targeting markets that require both complex software and high-performance data processing, such as automotive driver assistance, intelligent video surveillance, industrial automation, aerospace and defense, and next-generation wireless products.  (More)

Synfora’s PICO High-Level Synthesis Tool Achieves BDTI Certification By BDTI, 3/18/2010 BDTI recently completed an in-depth evaluation of Synfora’s PICO tool through the BDTI High-Level Synthesis Tool Certification Program™.  BDTI evaluated the process of implementing applications on a Xilinx FPGA using PICO, comparing it with traditional FPGA design based on hand-written RTL code, and with DSP processor software development.  PICO enabled creation of efficient FPGA implementations, with design productivity comparable to that of DSP processor software development.  The algorithmic C code required fewer modifications than the code that was used to implement the design on a DSP processor, while providing over a 30X improvement in price/performance. (More)

FPGA Start-Up Tabula Exits Stealth Mode, Unveils “3-D” Architecture and First Devices By BDTI, 3/18/2010 FPGA start-up Tabula recently emerged from stealth mode and disclosed details of its architecture, dubbed Spacetime, and product line, called the ABAX family. Tabula’s products are intended to compete against existing high-end FPGAs by offering higher density with the same design methodology.  Tabula is initially aiming its chips at network, wireless, and telecom infrastructure markets–all sweet spots for programmable logic.  These markets are characterized by a need for programmability due to rapidly changing standards, unit volumes too small to attract ASSP or ASIC competition, and relatively high gross margins for semiconductor suppliers. (More)

AutoESL’s AutoPilot High-Level Synthesis Tool Achieves BDTI Certification By BDTI, 2/16/2010 BDTI recently completed an in-depth analysis of AutoESL’s AutoPilot high-level synthesis tool via the BDTI High-Level Synthesis Tool Certification Program™. BDTI evaluated the process of implementing applications on a Xilinx FPGA using AutoPilot, comparing it with traditional FPGA design based on hand-written RTL code, and with DSP processor software development. Overall, AutoPilot demonstrated a strong ability to generate high-quality RTL code—with equivalent resource utilization to hand-written RTL code. (More)

BDTI Unveils High-Level Synthesis Tools Certification Program Results By BDTI, 1/20/2010 This week BDTI released the first results from its High-Level Synthesis Tools Certification Program (HLSTCP).  The first tools to achieve certification are AutoESL’s AutoPilot and Synfora’s PICO.  Additional certifications will be released on an ongoing basis, as agreements with tool vendors allow.  The HLSTCP helps engineers and managers understand the capabilities of high-level synthesis (HLS) tools and assess when to consider these tools for their designs.  HLS tool vendors can use the program to validate and improve the quality of results and productivity provided by their tools.  (HLS tools are also referred to as electronic system level [ESL] synthesis, C synthesis, behavioral synthesis, or algorithmic synthesis tools.) (More)

Synphony Synthesis Tool Takes MATLAB to RTL By BDTI, 10/21/2009 High-level synthesis tools (i.e., tools that take high-level language code and generate an RTL-based hardware implementation) have been around a long time, but historically they have had limited success in the market. The primary problems have been that they have been hard to use and have generated relatively inefficient implementations.  But their potential advantages are compelling, particularly as applications become more complicated: in the best case they can reduce implementation time and errors, and possibly reduce the need for RTL experts.  For these reasons, a number of vendors have introduced high-level synthesis tools in recent years, including AccelChip (later acquired by Xilinx), Mentor Graphics, Cadence, AutoESL, and Synfora, among others. Most of these take C representations as inputs and synthesize them into RTL for FPGA or ASIC implementation, though some have promised MATLAB to RTL. (More)

Xilinx Offers App-Specific Tool Bundles in ISE Design Suite Rev 11.1 By BDTI, 5/20/2009 In February when Xilinx announced its new Virtex-6 and Spartan-6 families, the company also discussed its intention to provide more domain-oriented development tools and development paradigms. In April the company began to make good on its promise by announcing domain-specific tool bundles as part of its new release of the ISE Design Suite, Rev 11.1. (More)

Xilinx Intros Spartan-6, Virtex-6; Promises App-Specific Development Support By BDTI, 2/18/2009 Xilinx recently introduced two new FPGA chip families, Spartan-6 and Virtex-6, that offer increased capacity and lower power consumption relative to their predecessors. For the first time, the new Spartan and Virtex families use the same underlying architecture to enable easier migration. There are, however, differences in fabrication process and features. Spartan-6 chips will be fabbed in a 45 nm process, while Virtex-6 chips will be fabbed in 40 nm.  Spartan-6 chips incorporate DDR3 integrated memory controllers and support for 3.3-volt I/O; Virtex-6 chips include specialized FIFO logic, tri-mode EMAC, and System Monitor. (The System Monitor is a debug and thermal management tool that was introduced in Virtex-5.) (More)

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