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| ARM Introduces Cortex-M4 Core for Digital Signal Controllers |
By BDTI, 7/29/2010
 This spring, ARM added the Cortex-M4 digital signal controller (DSC) to its processor core line-up. This product brings digital signal processing capabilities to ARM’s microcontroller core line (the Cortex-M family). At the Embedded Systems Conference in San Jose in April, NXP demonstrated a prototype Cortex-M4-based chip running at approximately 150 MHz. In June, Freescale announced its Kinetis line, also based on the Cortex-M4. ST Micro and Texas Instruments have also announced their intentions to use the Cortex-M4.
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| Freescale Takes on Texas Instruments with Multi-Core DSP Line |
By BDTI, 5/20/2010
 Freescale has announced a new high-performance DSP product line, the MSC825x, incorporating up to six StarCore SC3850 DSP cores at up to 1 GHz. Unlike other high-performance DSPs introduced by Freescale in recent years—which were aimed almost exclusively at wireless infrastructure applications—the new chips target a range of performance-intensive applications, including medical, aerospace and defense, and test and measurement equipment. This will put the new chips in direct competition with Texas Instruments’ (TI’s) high-performance multi-core DSPs (the TMS320C647x family, based on the C64x+ architecture).
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| Synfora’s PICO High-Level Synthesis Tool Achieves BDTI Certification |
By BDTI, 3/18/2010
 BDTI recently completed an in-depth evaluation of Synfora’s PICO tool through the BDTI High-Level Synthesis Tool Certification Program™. BDTI evaluated the process of implementing applications on a Xilinx FPGA using PICO, comparing it with traditional FPGA design based on hand-written RTL code, and with DSP processor software development. PICO enabled creation of efficient FPGA implementations, with design productivity comparable to that of DSP processor software development. The algorithmic C code required fewer modifications than the code that was used to implement the design on a DSP processor, while providing over a 30X improvement in price/performance.
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| AutoESL’s AutoPilot High-Level Synthesis Tool Achieves BDTI Certification |
By BDTI, 2/16/2010
 BDTI recently completed an in-depth analysis of AutoESL’s AutoPilot high-level synthesis tool via the BDTI High-Level Synthesis Tool Certification Program™. BDTI evaluated the process of implementing applications on a Xilinx FPGA using AutoPilot, comparing it with traditional FPGA design based on hand-written RTL code, and with DSP processor software development. Overall, AutoPilot demonstrated a strong ability to generate high-quality RTL code—with equivalent resource utilization to hand-written RTL code.
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| BDTI Unveils High-Level Synthesis Tools Certification Program Results |
By BDTI, 1/20/2010
 This week BDTI released the first results from its High-Level Synthesis Tools Certification Program (HLSTCP). The first tools to achieve certification are AutoESL’s AutoPilot and Synfora’s PICO. Additional certifications will be released on an ongoing basis, as agreements with tool vendors allow. The HLSTCP helps engineers and managers understand the capabilities of high-level synthesis (HLS) tools and assess when to consider these tools for their designs. HLS tool vendors can use the program to validate and improve the quality of results and productivity provided by their tools. (HLS tools are also referred to as electronic system level [ESL] synthesis, C synthesis, behavioral synthesis, or algorithmic synthesis tools.)
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| Case Study: Benchmarking PowerPoint Processors |
By BDTI, 8/26/2009
Processor designers know that a cycle-accurate simulator can be used to benchmark a processor that has not yet been fabricated. But many designers don’t realize that it’s also possible to benchmark an idea for a processor, a processor that may exist only in PowerPoint slides—and that there are good reasons for doing so.
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| BDTI Releases Benchmark Results for Toshiba's Venezia Platform |
By BDTI, 4/22/2009
 BDTI recently completed a benchmark analysis of the Toshiba MeP “Media embedded Processor” core and “IVC2” SIMD coprocessor, both of which are used in Toshiba’s Venezia mobile multimedia platform.
The MeP is a licensable core that is intended to be used as a building block in multi-core, multimedia-oriented SoCs, typically with multiple MeP cores on a chip. Each MeP core can be customized with specialized instructions, co-processors, and memory sizes.
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| BDTI Releases Benchmark Results for CEVA-Teaklite-III |
By BDTI, 2/18/2009
BDTI has released BDTI DSP Kernel Benchmarks™ results for the CEVA-TeakLite-III core from CEVA. As we’ve written previously, CEVA-TeakLite-III is a 32-bit DSP core that primarily targets audio applications (both portable and high-definition) but also targets VoIP and cellular baseband. It is the third generation of CEVA’s TeakLite architecture, and the first to use a native 32-bit data size. The CEVA-TeakLite-III also supports SIMD (single-instruction, multiple data) dual-16-bit MACs.
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| BDTI Releases Benchmark Results for CoreWorks DSP Engine |
By BDTI, 1/21/2009
BDTI has released BDTI DSP Kernel Benchmarks™ results for the SideWorks signal processing engine from CoreWorks, a Portugal-based vendor of licensable silicon intellectual property. SideWorks is a licensable DSP accelerator targeting cost and power-sensitive applications such as multimedia and communications. The core is both configurable (i.e., hardware resources included in a specific implementation are selected prior to fabrication) and reconfigurable (i.e., the movement of data and some aspects of execution unit functionality are programmable at run time). SideWorks is not designed to run as a stand-alone processor; it is intended to be coupled to a general-purpose “host” processor that manages program flow and data input/output. For this reason, BDTI’s benchmark results are implemented on a SideWorks core coupled to CoreWorks’ “FireWorks” CPU core.
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| BDTI Releases Benchmark Results for Sandbridge SB3500 |
By BDTI, 1/21/2009
 BDTI has released the first independent benchmark results comparing the performance of the Sandbridge “Sandblaster” SB3500 multi-core DSP chip to that of massively parallel chips, high-performance DSP processors, and FPGAs.
Sandbridge Technologies, Inc. is a fabless semiconductor company that sells multi-core chips targeting mobile 3G and 4G baseband and multimedia processing. The SB3500 chip includes three DSP cores along with an ARM core; each of the DSP cores supports four-way multithreading and 16-way SIMD operations. The SB3500 is implemented in a 65 nm process, and is available with the DSP cores running at either 500 or 600 MHz. The 500 MHz chip costs $25 in 1K quantities; pricing for the 600 MHz chip has not yet been disclosed.
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