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| Texas Instruments Introduces New Multi-Core System-on-Chip Architecture |
By BDTI, 2/16/2010
 TI has unveiled a new chip-level architecture for high-performance, multi-core DSP-processor-based SoCs. Most notable among its features are new on-chip and chip-to-chip interconnection mechanisms, an upgraded high-performance DSP core, and both hardware and tools support for programming concurrent applications. The architecture is optimized to run at 1.0 to 1.2 GHz in 40 nm process technology.
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| Multicore Heats up with Chip Announcements from TI, Tilera |
By BDTI, 11/18/2009
 Recently both Texas Instruments and Tilera announced new multicore chips. TI announced the TMS320C6472, which includes six ‘C64x+ processor cores running at 500-700 MHz (depending on the family member). Tilera announced a new chip family, the TILE-Gx, which will include variants with 16-100 cores running at 1.25-1.5 GHz. The ‘C6472 is available now, while Tilera does not expect to start sampling TILE-Gx chips until late 2010. According to Tilera, TILE-Gx chips will be fabbed in a 40 nm process. These announcements represent two of the common approaches to multicore today: putting a handful of processors that were originally designed for standalone use on a single die (TI) and creating a new architecture incorporating numerous cores (Tilera).
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| Tensilica Fills Out Portfolio with Dual-MAC DSP Core |
By BDTI, 9/6/2009
 This article has been modified from its original content. The original article contained a reference to the performance of the CEVA X-1620 core on a compiled C language implementation of the AMR-NB vocoder; this reference has been removed. These results were taken from a 2007 CEVA white paper. CEVA states that the X-1620 core is no longer offered for license and has been superseded by the CEVA X-1622. CEVA also states that the compiled-code performance results for the CEVA X-1622 on the AMR-NB vocoder are significantly better than those reported earlier for the CEVA X-1620. BDTI briefly reviewed CEVA’s new performance results, but in the limited time available BDTI was unable to confirm whether CEVA’s and Tensilica’s results are based on comparable test conditions and metrics.
This month Tensilica announced a new licensable DSP core, the ConnX D2. The D2 is an optional configuration of the Xtensa LX processor, and is a dual-MAC general-purpose DSP engine with communications-oriented enhancements. Unlike Tensilica’s recently announced high-performance baseband engine, the ConnX BBE, the D2 is a basic, entry-level DSP core designed for use in the many applications currently served by medium-performance processors like the CEVA TeakLite families and Texas Instruments ‘C55x. According to Tensilica, the core is currently being previewed with select customers, and will be production-ready in October.
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| Intrinsity, Samsung Announce Cortex-A8 “Hummingbird” |
By BDTI, 8/26/2009
 This month Intrinsity and Samsung jointly announced a new, highly optimized implementation of the ARM Cortex-A8 CPU core, called “Hummingbird.” According to Samsung and Intrinsity, an initial Hummingbird sample has achieved 1 GHz in Samsung’s 45nm low-power process. The companies say that Hummingbird is both faster and lower power than other Cortex-A8 implementations, though as of this writing they have declined to provide power data. Samsung says that it is currently developing Hummingbird-based SoCs for mobile products, but has not yet announced any products.
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| MIPS Positioning to Catch Android Wave |
By BDTI, 7/22/2009
 MIPS
recently announced that Android has been ported to the MIPS
architecture, with the goal of enabling its use in a variety of
consumer-oriented applications. Android is an open-source operating
system plus middle-ware and applications, and is backed by Google.
(Google acquired a small start-up called “Android”
in 2005, and continued development of Android software.) Android
was originally developed for use in handsets and was released in
open-source form in 2007 by the Open Handset Alliance, a group that
includes big-name mobile operators, handset vendors, semiconductor
vendors, and software houses.
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| Tensilica ConnX BBE Combines SIMD, VLIW for Baseband Performance |
By BDTI, 7/22/2009
 Last
month Tensilica unveiled the first member of its new “ConnX” family of
licensable DSP cores, the ConnX Baseband Engine (BBE), which combines
VLIW with SIMD to support a wide range of parallel operations. As part
of the announcement, Tensilica has also rebranded two of its existing
products: the Diamond 545CK core and Vectra DSP engine are now known as
the ConnX 545CK and ConnX Vectra, respectively. Tensilica says it has a
lead ConnX BBE customer that taped out a chip in June; the core will be
available for license in September. Speed, area, and power consumption
have not yet been disclosed.
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| New Details Emerge on NXP’s CoolFlux BSP Core |
By BDTI, 6/17/2009
 This month NXP has unveiled more details on its new licensable core, the CoolFlux BSP, which targets low-power communications baseband processing. The core is based on the similarly named CoolFlux DSP, which was designed for use in low-power audio applications and introduced in 2004. Relative to the older core, NXP says that the CoolFlux BSP has been enhanced to increase its performance in baseband processing while retaining a small footprint and low power.
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| OMAP 4 Ups Performance with Dual Cortex-A9 Cores |
By BDTI, 3/18/2009
 Texas Instruments recently announced its next-generation application processor family, OMAP 4. The OMAP 4 chip family targets smart phones and mobile internet devices (MIDs) and incorporates a number of distinct processing engines. General-purpose processing is provided via a dual-core SMP processor based on two ARM Cortex-A9 cores, both of which include the NEON multimedia extensions. As shown in Figure 1, OMAP 4 chips also include an imaging engine (TI’s ISP), graphics engine (Imagination Technologies’ POWERVR SGX540), programmable video engine (TI’s IVA3) and “audio backend engine” (TI’s ABE).
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| High-Performance CEVA-XC Core Targets 4G Handsets, Infrastructure |
By BDTI, 3/18/2009
 In February CEVA announced a new family of high-performance licensable DSP cores, the CEVA-XC family. CEVA-XC cores target 4G cellular applications, including LTE and WiMax, and are intended for use not just in handsets (as with previous CEVA cores) but also in infrastructure hardware. The CEVA-XC is an offshoot of the CEVA-X architecture (the “C” stands for communications), but the new core family is much more powerful than its predecessors. The highest-performance version supports, for example, up to 64 parallel multiply-accumulate (MAC) computations per cycle, compared to four for the CEVA-X1641. CEVA has not announced specific clock speeds, but says that it expects CEVA-XC to easily reach 500 MHz in a 65 nm process with a fully synthesizable design. Silicon area has not been disclosed.
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| Xilinx Intros Spartan-6, Virtex-6; Promises App-Specific Development Support |
By BDTI, 2/18/2009
 Xilinx recently introduced two new FPGA chip families, Spartan-6 and Virtex-6, that offer increased capacity and lower power consumption relative to their predecessors. For the first time, the new Spartan and Virtex families use the same underlying architecture to enable easier migration. There are, however, differences in fabrication process and features. Spartan-6 chips will be fabbed in a 45 nm process, while Virtex-6 chips will be fabbed in 40 nm. Spartan-6 chips incorporate DDR3 integrated memory controllers and support for 3.3-volt I/O; Virtex-6 chips include specialized FIFO logic, tri-mode EMAC, and System Monitor. (The System Monitor is a debug and thermal management tool that was introduced in Virtex-5.)
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