Editor’s Note: The past year or so has brought a wave of parallel-processor start-ups pursuing digital signal processing applications.  But what about the previous wave?  In the late 1990s and into 2001, a large number of start-ups emerged with unique processor architectures targeting applications like wireless infrastructure.  The vast majority of these, such as Chameleon, Morphics, and Quicksilver, are long gone.  PicoChip, founded in 2000, is an interesting exception.  In this article, BDTI provides an update on PicoChip’s status, technology and business model.

Headquartered in Bath, UK, picoChip is a fabless semiconductor company developing high-performance chips for wireless infrastructure applications.  Devices from picoChip contain roughly 300 processor cores and target 3G cellular and WiMAX base stations. PicoChip claims to have shipped 100,000 chips and says that over 100 WiMAX networks are committed to using picoChip-based equipment.  If so, picoChip is one of the few massively parallel processor companies to have shipped chips in volume.

Processor cores and hardware accelerators in picoChip’s multiple-instruction, multiple-data (MIMD) architecture communicate with each other via 32-bit buses using a time-division multiplexed scheme. All logic operates from a single clock. To implement an application, the programmer decomposes the application into components (sets of processes) communicating via signals. Structural VHDL is used to specify the signal data types and signal bandwidth constraints; implementation of the processes—the majority of the coding effort—is done in ANSI C or assembly. After compilation by the provided C compiler, the programmer specifies the distribution of processes across processors. A place-and-route tool then maps the processes onto specific processors. PicoChip also provides users with a visual tool enabling a block-diagram view of the design, a simulator, and probes allowing monitoring of system behavior.

Massively parallel multi-core processors have traditionally raised concerns of programming complexity, interprocessor communication bottlenecks, and non-deterministic execution.   (Regarding non-determinism, see, for example, Edward Lee’s paper “The Problem with Threads”.) In picoChip’s design, processing elements are kept simple, to simplify programming and distribution of processes. The assignment of processes to processors and the patterns of interprocessor communication are fixed at compile time: no bus contention issues remain to be resolved during actual execution. Each processing element relies primarily on its local memory to implement the functionality mapped on to it; when local memory is insufficient, access to the external SRAM is under the control of the programmer. In addition, the debugging tools provide visibility into the entire chip. PicoChip claims that these factors make developing and debugging of complex applications manageable, despite the large number of processors involved. “Standard DSPs are like quantum physics, probabilistic and only statistically predictable: each run has slightly different timing, and every time you look at it, you see a different state. The picoArray (picoChip’s nomenclature for its array of processing elements) is like billiard-ball physics: if you run the same code again, you will get the same timing and the same state,” says Rupert Baines, VP of Marketing at picoChip. (For details on picoChip’s approach to deterministic design, see picoChip’s paper,  “Deterministic Parallel Processing”).